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test
- Verilog HDL SDRAM controller
Sdram_Control_4Port
- 用Verilog写的SDRAM的控制器的代码，分为详细实现了对SDRAM的控制-Written using Verilog code for SDRAM controller is divided into in detail to achieve the control of SDRAM
sdram_control
- 基于FPGA对sdram控制器的设计（VERILOG语言）-sdram fpag verilog
sdram_controller
- SDRAM控制器 SDRAM控制器 SDRAM控制器-verilog
61EDA_D556
- FPGA中的SDRAM的设计，用VERILOG语言设计-fpga sdram
sdramc_controller
- sdram 控制器 用verilog语言实现 可综合-sdram controller can be integrated with the verilog language
rtl
- 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design
SDRAMtest
- 使用quartus软件打开 内含sdram测试文件代码语言为verilog 备注清晰，适合初学者-Quartus software using open source test file containing sdram verilog Remarks clear language, suitable for beginners
sdram_hr_hw
- SDRAM 读写控制检测Verilog源代码程序。-SDRAM read and write Verilog source code control testing procedures.
sdr_verilog_lattice
- Verilog控制SDRAM-Verilog control SDRAM
sdram_control
- 基于硬件语言Verilog的一个sdram控制器的设计以及仿真-Verilog language, a hardware-based controller design and simulation sdram
SDRAM1
- 这是一个控制sdram的程序，用verilog编写的-This is a control program sdram, prepared with verilog
source
- 本源码是 基于VERILOG的SDRAM的开发与实现 并能实现 刷新，预充电，突发长度为8字节等功能 已验证，可用-The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available
project1_supplemental1
- these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..
83399055ref-sdr-sdram-verilog
- Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences,
sdr_test
- sdram读写测试程序，带modsim仿真文件-verilog code of reading and writing of sdram, with modsim simulation test file.
SDRAM_TEST
- 用Verilog硬件描述语言驱动SDRAM，内有完整可实现源代码，且还有现象说明-With the Verilog hardware descr iption language driven SDRAM, can be realized within the complete source code, and there is the phenomenon described
tut_DE1_sdram_verilog
- a complete tutorial on the sdram a verilog code
sdram_vhdl
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Source
- I2C 控制器的 Verilog源程序以及I2C规范说明-The I2C bus provides a simple two-wire means of communication. This protocol is used in many applications.SDRAM modules implement a serial EEPROM that supports the I2C protocol. This is used so that a micro